First of all, my experiment is described as follows:
with single-chip SPI and GPIO, MOSI, MISO, SCLK, CSN, and IRQ_GP3 pick heel ADF7023 connection.
firmware running on a single-chip-based "http://www.analog.com/static/imported-files/eval_boards/ADF7023_DeviceDrivers.zip" an official example, single-chip can read "Status Word" may interpret the IRQ and state of the ADF7023.
c to the Advance Encryption Standard (AES) - By Kalim Khan (RFG Cork), pdf description file, "rom_ram_7023_2_2_RS_AES.dat module two files, to proceed with the implementation and testing of the AES encryption and decryption functions.
Then, my question are as follows:
1 implementation of AES encryption and decryption procedures to before CMD_CONFIG_DEV issued or after it?
2 file "patch RAM" is the ADF7023 information manual "program RAM"? If so, wishing loading of modules required to fill in the address is not 0x1000 (binary 1000000000000)? If so, you need to command value 0x1E with 0x1000 together?
Following documentation the 0x18 command value to populate the packet RAM ", and with the information booklet on the memory map section to control, not the encryption and decryption of payload only up to 70 bytes? Or is it every time you encrypt or decrypt the payload is only 16 bytes?
4 after the command wait 10 milliseconds, is a fixed period? Or a single chip to determine the "Status Word" the "FW_STATE" field is "Busy"? Or there will be a different approach?
Implementation of AES encryption and decryption procedures will with official sample configuration set conflict? I need to follow to modify PACKET_LENGTH_MAX, TX_BASE_ADR, or RX_BASE_ADR register it? If yes, the value of the register how to modify it?
If you need only use the AES ECB mode, you can not fill value to the initialization vector block? Or special value must be filled?
7. Perform AES encryption and decryption process, can normally send and receive packets?
8 to perform AES encryption process can simultaneously AES decryption ?